1. Field of the Invention
This invention relates to an offset adjusting apparatus for canceling an offset voltage generated in a difference amplifier.
2. Description of the Prior Art
FIG. 5 is a circuit diagram showing an operational amplifier to which a conventional offset adjusting apparatus is applied. In the figure, reference numeral 1 denotes a differential head section including a difference amplifier of the operational amplifier. Numeral 2 denotes a current mirror section including another difference amplifier of the operational amplifier. Numeral 3 denotes an output stage circuit of the operational amplifier. Numeral 4 denotes a capacitor for phase compensation.
Reference character Tr1 denotes a transistor for supplying a constant current. Characters Tr2 and Tr3 denote transistors of the differential head section 1. Characters Tr4 and Tr5 denote transistors of the current mirror section 2. Characters Tr6 and Tr7 denote transistors of composing the output stage circuit 3.
FIG. 6 is a circuit diagram showing a conventional offset adjusting apparatus shown in, for example, JP-Sho. 59-67705. In the figure, reference numeral 5 denotes a transistor group for adjusting an offset voltage, including transistors A1-An connected in parallel to each other. Numeral 6 denotes a selection switch for controlling the turning on and off of the transistors A1-An.
Next, the operation of the prior art will be described.
If specific characteristics, such as a threshold voltage and variations in designed size, of the transistors Tr2 and Tr3, of the differential head section 1, completely accord with each other, and if specific characteristics of the transistors Tr4 and Tr5, of the current mirror section 2, completely accord with each other, an offset voltage generated in the operational amplifier is 0 mV under a condition that the resistance of wiring is distributed unsymmetrically in its layout.
However, it is actually almost impossible to produce those transistors so that the above-mentioned specific characteristics of the transistors are completely equal to each other and that the resistance of wiring is distributed completely unsymmetrically in a production process of a semiconductor integrated circuit using a wafer process. As a result, an offset voltage is usually generated.
Accordingly, when an offset voltage generated in an operational amplifier is required to be cancelled, conventionally, transistor groups 5 are connected in parallel to the transistors Tr4 and Tr5 in the current mirror section 2, respectively, and further the on-resistance of the transistor Tr4 or Tr5 is adjusted by switching the on-off states of transistors A1-An of the transistor groups 5 with the selection switch 6 for canceling the generated offset voltage.
That is, when the on-off states of the transistors A1-An are switched, the on-resistance of the transistor Tr4 or Tr5 is changed to vary the gate voltage of the transistor Tr7. As the on-resistance of the transistor Tr7 is varied consequently, the output voltage of the output stage circuit 3 can be adjusted.
Therefore, the offset voltage can be canceled by switching the on-off states of the transistors A1-An.
Because the conventional offset adjusting apparatus is constructed as above, the accuracy of cancellation of an offset voltage can be improved in the transistor groups 5 by connecting a lot of transistors having an appropriate size in parallel to each other. However, there is a problem that the layout size of the transistor groups 5 is large due to their large circuit scale in such cases where the gates of the transistors Tr4 and Tr5 are designed to be wide because their threshold voltages are low and where the transconductances of the transistors Tr4 and Tr5 are relatively small.